c opyright @ 2011 jmicron technology crop . all rights reserved. nda required product brief version 1.0 2011/03/01 jm f60 5 JMF605 arm base sataii to flash controller overview jmf 605 is a single chip, supports sata ii to nand flash interface. it is native design to provide higher bandwidth for flash memory access. jmf 605 can support the maximum read and write speed to drive th e limit of flash memory. jmf 605 has the best supporting to the latest nand flash memory, including sam s ung, toshiba, hynix , micron and i m flash. it also provides the embedded hardware error correction code (ecc), wear leveling, and bad block manage ment tec hnology in th is chip. in order to resolve compatibility issue, jmf 605 provides the on line firmware upgrade ability. jmf 605 provides embedded processor , internal masked rom, data sram, sata link/transport layer, sata phy . data swap between different inter faces can be done very efficiency by dma without cpu involvement. based on the efficient architecture, the jmf 605 can provide the best performance . features compliance ? compliant with serial ata international organization: seri al ata revision 2. 6 . sata i/ ii ? supports 1 - port 1.5/ 3.0gbps sata i/ii interface . cpu ? embedded processor. ? embedded masked program rom . ? embedded system ram . flash ? supports maximum ces to 16 ces. ? support 5x/4x/3x /2x n m flash ? enhanced endurance by d ynamic /static wear - leveling . ? s uppor ts 4k /8k bytes page size. ? s upport s dynamic power management . ? smart (self - monitoring, analysis and reporting technology) . www.datasheet.co.kr datasheet pdf - http://www..net/
c opyright @ 2011 jmicron technology crop . all rights reserved. nda required product brief version 1.0 2011/03/01 jm f60 5 ? data integrity under power - cycling . ? supports 8 bit s flash interface . ? s upport s bch ecc 16 b it s or 24 bits in 1024 bytes system ? integrated 1 - sata ii port and 4 - channel s flash controller . ? led indicator for sata r ead/write access . ? led indicator for sata phy link up. ? provides 8 gpio pins for customer . ? provides uart and jtag for s/w debugging . ? built - in pow er - up self - test (bi s t) . ? manual and automatic self - diagnostics . ? provides voltage low detect interrupt. ? 130 - ball l fbga package. firmware ? support ncq on this controller. ? s upport lba24 & lba48 on this controller . ? support 1 to 8 bank s selected free . ? suppo rt 2 to 4 channels selected free. www.datasheet.co.kr datasheet pdf - http://www..net/
c opyright @ 2011 jmicron technology crop . all rights reserved. nda required product brief version 1.0 2011/03/01 jm f60 5 block diagram figure 1 : j mf 605 block diagram total capacity table 1 : jmf 605 total capacity table density/per flash support ce pins/per flash maximum flash number total capacity 1g x 8 bits (8gb) 1 ce pin 16 16 g bytes 2g x 8 bits (16gb) 1 ce / 2 ce pin 1 6 32 g bytes 4g x 8 bits (32gb) 1 ce / 2 ce pin 16 64 g bytes 8 g x 8 bits ( 64 gb) 2 ce pin 16 128 g bytes 16 g x 8 bits ( 128 gb) 4 ce pin 8 128 g bytes www.datasheet.co.kr datasheet pdf - http://www..net/
c opyright @ 2011 jmicron technology crop . all rights reserved. nda required product brief version 1.0 2011/03/01 jm f60 5 product information name de scription JMF605 arm base sata - ii to flash controller document 1 JMF605 data sheet 2 JMF605 specification 3 JMF605 h ardware design guide 4 JMF605 hardware sehcmatic cont act inf ormation department email sales s ales@jmicron.com tech. support fae@jmicron.com www.datasheet.co.kr datasheet pdf - http://www..net/
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